1. Field of the Invention
The present invention relates to a high level synthesis method for a semiconductor integrated circuit, and more specifically to a high level synthesis method for a semiconductor integrated circuit for performing high level synthesis in consideration of a layout.
2. Description of the Background Art
With the spread of increasingly efficient use of information in the society and the development of information technology for supporting such a tendency, information processing functions of electronic devices have been remarkably enhanced. In electronic devices, large scale integrated circuits play a central role for realizing information processing functions. Research and development of ultra-fine and high-precision technologies have been actively performed as process technologies for producing large scale integrated circuits providing higher performance with more complicated structures and lower power consumption at lower cost. On the other hand, for technologies for designing large scale integrated circuits with less work in a shorter period of time, research and development have been performed in a wide range of technologies from highly abstract high level designing to logic circuit synthesis technologies using support by software, physical circuit synthesis technologies, and technologies for using existing circuit designs.
The following problems are described in Lavi Lev and one other, Eedesign, “Right on time—requirements for advanced custom design” (searched on Jun. 1, 2004 in the Internet (URL: http://www.eedesign.com/story/OEG20030822S0027), Aug. 22, 2003). Recent process technologies have reached nano-scale structures and voltage reduction has been advanced. As a result, physical effects, which could be estimated with sufficient precision or could be ignored in circuit designs using the conventional process technologies now cause problems. For example, recent, highly precise semiconductor integrated circuits conspicuously present the influences of charge capacitance parasitic between lines, line resistance, signal interference between electronic circuits (crosstalk, noise, etc.), voltage drop, and the like. The degree of influence of these factors is not known with certainty. For these reasons, it is now difficult to complete layout design and physical design, which are the final stages of circuit design, with certainty.
As described above, while more abstract design technologies are desired for efficiently designing large scale integrated circuits on one hand, the difficulty in guaranteeing completion of circuit design is becoming serious on the other hand.
In order to solve this problem, a method of repeating the steps of high level design to physical design many times is provided. However, this solution is not practical because these two design steps are significantly time-consuming. Recently, a method of performing simple, provisional layout processing in the high level design process is proposed in order to estimate the minimum necessary physical properties.
For example, a high level design method for estimating the layout result in a simple manner as shown in FIG. 44 is proposed in the following two documents: William E. Dougherty and one other, “Unifying Behavioral Synthesis and Physical Design”, Proceedings for the 37th Design Automation Conference (2000); and Junhyung Um and two others, “Layout-Driven Resource Sharing in High-Level Synthesis”, Proceedings for International Conference on Computer Aided Design (2002). According to the high level design method shown in FIG. 44, a CDFG generation step, an initial allocation scheduling step, a resource arrangement step, and a resource sharing step are performed for operation description data describing the operation specifications of a semiconductor integrated circuit to be designed.
First, in the CDFG generation step (step S11), a graph referred to as a “CDFG” (Control Data Flow Graph; see FIG. 2 described later) is generated based on input operation description data. The CDFG includes a DFG (Data Flow Graph) representing a flow of calculations and data and a CFG (Control Flow Graph) representing execution control of calculations.
Next, in the initial allocation scheduling step (step S12), an allocation schedule (see FIG. 3 described later) and an allocated resource connection graph (see FIG. 4 described later) are generated based on the CDFG generated in the CDFG generation step. The allocation schedule indicates to which clock cycles the processing nodes included in the CDFG are allocated. The allocated resource connection graph is a graph in which nodes represent hardware resources allocated to the processing nodes of the CDFG (hereinafter, referred to as the “allocated resources”) and edges represent flows of signals in the CDFG. The CDFG generation step and the initial allocation scheduling step will be described in a first embodiment of the present invention.
Next, in the resource arrangement step (step S13), a rough arrangement of the allocated resources in a provisional layout area is determined based on the allocated resource connection graph generated in the initial allocation scheduling step. This step uses the allocated resources as the nodes as elements to be arranged, and the edges of the allocated resource connection graph as connection elements between the elements to be arranged. In the resource arrangement step, a simplified arrangement technique is used, instead of a precise technique for arranging the elements to be arranged having a determined shape, which is used in a general physical design step (for example, the arrangement technique of standard cells). Specifically, a relative positional relationship when the allocated resources are represented with points having no size is obtained, and then an arranged position of each element to be arranged in the provisional layout area is determined.
Finally, in the resource sharing step (step S14), when a plurality of allocated resources having the same function are arranged close to each other in the layout result, such allocated resources are shared in consideration of the processing timing. This is conducted in order to reduce the number of allocated resources. The allocated resources can be shared for the following reasons. When there are a plurality of allocated resources having the same function, a plurality of allocated resources operating at different clock cycles can be replaced with one of the allocated resources by making the resource operate at these different clock cycles. Then, the other allocated resources are unnecessary.
As a result of sharing, the number of allocated resources is decreased. This can reduce the circuit area. By sharing allocated resources in consideration of the relative positions in the layout, the allocated resources can be shared with no specific difficulty after the layout design, and as a result, high level design with highly precise estimation of the physical design can be performed.
However, the above-described conventional sharing method has the following problems. According to the conventional sharing method, allocated resources are provisionally arranged using an allocated resource connection graph. When a plurality of allocated resources having the same function are arranged close to each other by chance in the layout result, such allocated resources are shared. This method does not consider the allocation schedule obtained in the initial allocation scheduling step. Therefore, when the allocated resources having the same function which are arranged close to each other are shared, the allocation schedule may be changed, which may result in a situation where given design specifications cannot be fulfilled.
One possible solution to this problem is to perform the initial allocation scheduling step with timing conditions which are more stringent than the design specifications (i.e., with higher-speed operation conditions). However, introduction of such an unnecessarily high performance requires more hardware resources and thus increases the circuit area and power consumption. As a result, an optimum circuit cannot be provided.